Walkin Interview @ Infotech Enterprises in Bangalore on 5th & 6th November 2011 (Stress Analysis & ASIC)

Company : Infotech Enterprises (www.infotech-enterprises.com)

 

Walk-in Drive at Bangalore for Stress Analysis & ASIC Requirements on 5th & 6th November 2011

 

Walk-in Venue: Hotel Grand Krishna, #77, Hosur Main Road, Near Ayyappa Temple, Madiwala, Bangalore-560068, Contact No's: 080-25525723/4/ 09246372722.  Walk-in Time: 10.00 AM to 3.00 PM.

Please refer your friends, relatives and acquaintances for these opportunities. The Job Description for these positions are mentioned below.

 

Note: All these requirements will be covered under the newly Enhanced Referral Policy,  only if the profiles are sent to HR directly. Candidates who have attended interview with Infotech in the last 6 months are not eligible.

 

 

Stress Analysis Requirements

 

Aero Structures Analysis - Nastran/Patran/Hand Calculations: (Job Code: ASA)

 

Experience: 3 - 10 years' in Aircraft structures, preferably in any one of the following areas:

 

• Analysis of Primary & Secondary (Fuselage, Wing, Empennage) structures.
• Knowledge and hands-on experience in Stress analysis (Composite & Metallic) and to check the detailed stress analysis as per any OEM standards.
• Knowledge and hands-on experience in Fatigue & Damage Tolerance analysis (Composite & Metallic).
• Working knowledge of Patran/Nastran, Abaqus, MathCAD, Excel VBA will be an added advantage.

 

Job Location: Hyderabad/Bangalore

 

 

Structural Analysis Engineers - Ansys/Nastran/ Patran/Hypermesh/Abaqus: (Job Code: SAE)

Experience: 3 - 8 years' in finite element modelling, analysis and post processing.

• Candidates should have hands-on experience with various analysis types such as linear statics, non-linear statics (contact, material and large deformation), dynamics (normal modes and cyclic modal) etc. Expertise in 2D/3D FE modeling in Ansys or NX- CAE or Hypermesh or Patran/Nastran or LS Dyna or Abaqus, for aero-engine/turbo-machinery/automotive/heavy engineering components is preferred.
• Experience in interpreting and understanding FEA results, post-processing, suggesting alternative design solutions and preparing comprehensive analysis reports are expected.
• Experience in ANSYS work bench, ANSYS APDL, TCL and TK  experience to write macros in HM, assembly modelling or 3D Meshing using brick elements would be added advantage.

Job Location: Hyderabad

 

 

ASIC Requirements

 

ASIC VERIFICATION  (Job Code: ASIC-V)

Experience: 2 to 10 years' experience in the following areas:  

 

Multiple skills required:

Expertise in System Verilog & OVM .

Expertise in System Verilog & e-specman.

Expertise in Mixed Signal Verification.

 

Job Location: Hyderabad & Bangalore

 

ASIC PHYSICAL DESIGN  (Job Code: ASIC- PD)

Experience: 2 to 10 years' experience in the following areas:  

 

Partitioning, IO ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design.

 

Job Location: Hyderabad ,Bangalore, Vizag & Noida.

 

ASIC IMPLEMENTATION (Job Code: ASIC-IMP)

Experience: 2 to 10 years' experience in the following areas:  

 

Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.

 

Job Location: Hyderabad ,Bangalore & Noida.

 

ASIC DFT  (Job Code: ASIC-DFT)

Experience: 2 to 10 years' experience in the following areas:  

 

•  Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools.
• Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
• Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
• Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
• Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug.
• Programming in Perl, tcl, awk and c/c++.  
• Experience in DFT with Logic Vision tools is mandatory.

 

Job Location: Hyderabad ,Bangalore & Vizag .

 

FPGA Engineers  (Job Code: FPGA)

Experience: 2 to 10 years' experience in the following areas
 

Ability to interface with silicon companies and understand their requirements and expectations.

• Rapidly adapt to different design and verification environments
• Coordinate efforts with offshore design and verification teams
• Strong experience using System Verilog & OVM / VMM
• Experience in Test Benches
• ACTEL based experience would be an added advantage

 

Job Location: Hyderabad
 

 

Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams.

 

Candidates who are unable to attend the drive can forward their resumes mentioning "Job Code & Years of Experience" in the Subject line to: Praveen.Vemula@infotech-enterprises.com for ASIC requirements &  Kiran.Chettigari@infotech-enterprises.com for Stress Analysis requirements.

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