Thursday, September 29, 2011

Walkin Interview @ Infotech Enterprises in Bangalore on 1st & 2nd October 2011

Company : Infotech-Enterprises Limited (www.infotech-enterprises.com)

 
We are conducting Walk-in Drive at Bangalore for Stress Analysis & ASIC Requirements on 1st  & 2nd  October 2011 (Saturday & Sunday). 
 
Walk-in Venue: Hotel Grand Krishna, #77, Hosur Main Road, Near Ayyappa Temple, Madiwala, Bangalore-560068, Contact No's: 080-25525723/4/ 09246372722.  Walk-in Time: 10.00 AM to 3.00 PM.
Please refer your friends, relatives and acquaintances for these opportunities. The Job Description for these positions are mentioned below.
 
Note: . Candidates who have attended interview with Infotech in the last 6 months are not eligible.
 
 
Stress Analysis Requirements
 
Aero Structures Analysis - Nastran/Patran/Hand Calculations:(Job Code: ASA)
 
Experience: 3 - 10 years' in Aircraft structures, preferably in any one of the following areas:
 
  • Analysis of Primary & Secondary (Fuselage, Wing, Empennage) structures.
  • Knowledge and hands-on experience in Stress analysis (Composite & Metallic) and to check the detailed stress analysis as per any OEM standards.
  • Knowledge and hands-on experience in Fatigue & Damage Tolerance analysis (Composite & Metallic).
  • Working knowledge of Patran/Nastran, Abaqus, MathCAD, Excel VBA will be an added advantage.
 
Job Location: Hyderabad/Bangalore
 
Structural Analysis Engineers - Ansys/Nastran/ Patran/Hypermesh/Abaqus: (Job Code: SAE)
Experience: 3 - 8 years' in finite element modelling, analysis and post processing.
  • Candidates should have hands-on experience with various analysis types such as linear statics, non-linear statics (contact, material and large deformation), dynamics (normal modes and cyclic modal) etc. Expertise in 2D/3D FE modeling in Ansys or NX- CAE or Hypermesh or Patran/Nastran or LS Dyna or Abaqus, for aero-engine/turbo-machinery/automotive/heavy engineering components is preferred.
  • Experience in interpreting and understanding FEA results, post-processing, suggesting alternative design solutions and preparing comprehensive analysis reports are expected.
  • Experience in ANSYS work bench, ANSYS APDL, TCL and TK  experience to write macros in HM, assembly modelling or 3D Meshing using brick elements would be added advantage.
Job Location: Hyderabad
ASIC Requirements
 
ASIC VERIFICATION:  (Job Code: ASIC-VE)
Experience: 2 to 10 years' experience in the following areas:  
 
Multiple skills required:
  • Expertise in System Verilog & OVM .
  • Expertise in System Verilog & e-specman.
  • Expertise in Mixed Signal Verification.
  • Expertise in Low Power Design Verification.
  • SOC Verification with ' C ' based Verification Environment.
 
Job Location: Hyderabad & Bangalore
 
LOGIC DESIGN: (Job Code: ASIC-LD)
Experience: 3 to 10 years' experience in the following areas:  
 
He/She should be able to come up with microarchitecture of chip/block from high-level architecture.  Should have expertise in logic design, RTL coding, module level verification and debug, basic understanding on timing closure, constraints, interacting with backend/DFT teams to close DFT/timing related issues.
 
Job Location: Hyderabad & Bangalore
 
 
ASIC PHYSICAL DESIGN:  (Job Code: ASIC- PD)
Experience: 2 to 10 years' experience in the following areas:  
 
Partitioning, IO ring preparation, Floor Planning, PG planning, Place and Route, Clock Tree Synthesis, Timing Closure, Static Timing Analysis, IR drop analysis, Physical verification, Signal Integrity, Low Power design.
 
Job Location: Hyderabad ,Bangalore, Vizag & Noida.
 
ASIC IMPLEMENTATION (Job Code: ASIC-IMP)
Experience: 2 to 10 years' experience in the following areas:  
 
Logic Synthesis, Low Power Synthesis, Timing Constraints, Timing Closure, Static Timing Analysis, Cross talk analysis and Repair, Formal Verification.
 
Job Location: Hyderabad ,Bangalore & Noida.
 
ASIC DFT  (Job Code: ASIC-DFT)
Experience: 2 to 10 years' experience in the following areas:  
 
  •  Basic logic design, Verilog RTL and verification back ground with exposure to STA utilizing industry standard tools is good to have.
  • Must possess a strong knowledge of DFT including JTAG, Boundary scan, MBIST, LBIST, scan, on-chip scan compression, fault models, ATPG, and fault simulation and AC scan for at speed testing.
  • Expertise in industry standard EDA tools for DFT such as DFTAdvisor, fastscan/TestKompress, TetraMax, LogicVision.
  • Experience in Full-Chip DFT implementation of Scan, EDT/Adaptive Scan, JTAG, MBIST, Transition and Path delay ATPG.
  • Experience in Gate Level Simulations, Synthesis, STA and Formal Verification. Understanding of ATE and test engineering. Post-Silicon debug.
  • Programming in Perl, tcl, awk and c/c++.  
  • Experience in DFT with Logic Vision tools is good to have.
 
Job Location: Hyderabad ,Bangalore & Vizag .
 
 
CUSTOM LAYOUT: (Job Code: ASIC-CL)
Experience: 4 to 10 Years
 
Basic:
  • Expertise in Custom Layout Standard Cells, I/O or special analog designs such as RF transceivers,  PLL, DLL, LDO, Bandgap, VCO, ADC,DAC
  • Strong Layout Design Concepts
  • Experience in Layout Design tools such as Virtuoso, Virtuoso-XL
  • Expertise in SKILL Programming Language
  • Experience in Physical verification
 
Job Description:
  • He/She should be able to work on analog layout, physical verification on blocks under a tech lead or a senior custom layout engineer. The candidates should have a strong expertise in some critical layouts such as PLL, DLL, LNA, VGA, ADC, LDO.
  • He/She should be able to adapt to new technologies/tools/flows pretty quickly.
 
Job Location: Hyderabad & Bangalore

 
FPGA Engineers:  (Job Code: FPGA)
Experience: 3 to 8 Years
 
FPGA verification experience: Experience: 3 to 8 Years
 
  • Strong experience with System Verilog and OVM, UVM, VMM, or eRM methodologies
  • Experience to implement, evaluate, debug, and improve a verification environment
  • ACTEL based experience would be an added advantage.
  • GOOD communication and documentation skills
  • Experience in handling protocols is a plus
  • Rapidly adapt to different design and verification environments
  • Knowledge on D0-254 will be an advantage
 
Job Location: Hyderabad
 
 
 FPGA system level design experience: Experience: 3 to 8 Years
 
  • Experience in complete FPGA design cycle including verification
  • Verilog, VHDL experience
  • Experience with any of the tools like: Quartus II, SOPC Builder / Xilinx ISE / Actel Libero.
  • Simulations and on-chip debugging capabilities and board testing capabilities
  • Exposure to Multi-FPGA Design Partitioning
  • Experience in Gigabit Ethernet, PCI-Express is desirable
  • Familiarity with CAN, LIN, Flexray will be an advantage
  • Experience in automotive grade electronics design is an advantage
 
Job Location: Hyderabad
 
 
Qualification for all the above positions: BE/B.Tech or ME/M.Tech/MS in respective streams.
 
Candidates who are unable to attend the drive can forward their resumes mentioning "Job Code & Years of Experience" in the Subject line to: Praveen.Vemula@infotech-enterprises.com for ASIC requirements &  Kiran.Chettigari@infotech-enterprises.com for Stress Analysis requirements.
 
Candidates need to carry relevant documents for the interview: Latest resume, academic qualification documents, Experience certificate, Latest 3 months payslips pay slips, etc.

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